Measurement and Characterization of Multilayered Interconnect Capacitance for Deep-Submicron VLSI Technology
نویسندگان
چکیده
This paper presents the measurement and characterization of multilayered interconnect capacitances for a 0.35m CMOS logic technology, which become a critical circuit limitation to high performance VLSI design. To measure multilayered capacitances of nonstacked, stacked, and orthogonally crossing interconnect lines, new test structures and measurement method are presented. The measured interconnect capacitances were employed to evaluate and calibrate TCAD tools for the simulation of high-speed interconnect technologies. This study shows that the calibration method considerably improves the accuracy of simulation results compared with measured results.
منابع مشابه
Modeling the Effect of Wire Resistance in Deep Submicron Coupled Interconnects for Accurate Crosstalk Based Net Sorting
It is well known that in deep submicron technologies the coupling capacitance between adjacent wires is a critical portion of the total wire capacitance, while at the same time the capacitance between wire and substrate has become the fringing component. High frequency signals travelling across multiple level interconnect structures generate proximity effects, i.e. crosstalk effects, between ad...
متن کاملEffect of Line Parasitic Variations on Propagation Delay in Global VLSI Interconnects
Process variation is considered to be a major concern in the design of circuits including interconnect pipelines in current deep submicron regime. Process variation results in uncertainties of circuit performances such as propagation delay. The performance of VLSI/ULSI chip is becoming less predictable as device dimensions shrinks below the sub-100-nm scale. The reduced predictability can be at...
متن کاملModeling and Layout Optimization of VLSI Devices and Interconnects In Deep Submicron Design
This paper presents an overview of recent advances on modeling and layout optimization of devices and interconnects for high-performance VLSI circuit design under the deep submicron technology. First, we review a number of interconnect and driver/gate delay models, which are most useful to guide the layout optimization. Then, we summarize the available performance optimization techniques for VL...
متن کاملCrosstalk Delay Analysis in Very Deep Submicron VLSI Circuits
The evolution of Integrated Circuit designing has been a real game changer in the field of VLSI system in the past quarter century. Very deep sub-micron (VDSM) technologies embracing sub-100nm wafer design technologies, to take advantage of the superior integration possibilities. At these technologies, many phenomena affect gate, path delay or wire delays. Now a days, crosstalk noise or crossta...
متن کاملDeep Submicron VLSI Floorplanning Algorithm
In deep submicron VLSI designs, cross capacitance between adjacent wires becomes the dominant factor in determining chip performance and power consumption. Consequently, traditional floorplanning algorithms, which typically optimize for die area and ignore wire congestion, become inadequate in deep submicron era. Based on a stochastic congestion model, we propose a floorplanning algorithm that ...
متن کامل